1. Field of the Invention
The present invention relates to a PLL (phase-locked loop) apparatus.
2. Description of the Related Art
A conventional PLL apparatus includes a voltage controlled oscillator (VCO) for providing an output signal, and a phase-locked loop formed of a frequency divider for frequency-dividing the output signal from the VCO with a predetermined ratio to convert the VCO output into a predetermined frequency signal, a clock generator for generating a reference clock signal having the predetermined frequency, a phase detector for detecting a phase difference between an output signal from the frequency divider and the reference clock signal, and a loop filter for applying a control voltage to the VCO in accordance with the phase difference. More specifically, the PLL loop controls the control voltage for the VCO until the phases of the output signal from the frequency divider and the reference clock signal coincide with each other, i.e., a phase-locked state is set. The loop filter is formed of a resistor and a capacitor. The phase detector charges or discharges the capacitor depending on whether the phase difference is positive or negative, and supplies a potential difference across the capacitor to the VCO as the control voltage.
When a phase-locked state is set, an output from the phase detector, i.e., an input terminal of the loop filter is set in a high-impedance state. This state is the same as a state wherein nothing is connected to the input terminal of the loop filter. Therefore, even if a power source for supplying power to circuits except for the VCO is turned off in the locked state, the control voltage for the VCO is not changed. A frequency of the output signal from the VCO is not changed, and the phase-locked state can be kept. Such driving is so-called "intermittent PLL driving", and is often performed to save power of a power source for the PLL apparatus.
In practice, however, a leakage current flows through the capacitor. Therefore, when the intermittent PLL driving is performed and the power source for circuits except for the VCO is turned off, the terminal voltage of the capacitor in the loop filter is gradually decreased, and an oscillation frequency of the VCO is gradually changed.
Thus, in the conventional PLL apparatus, the terminal voltage of the capacitor in the loop filter directly changes the oscillation frequency of the VCO. Therefore, when the power source for circuits except for the VCO is turned off to save power in the phase-locked state, the terminal voltage of the capacitor is decreased due to the leakage current of the capacitor, and the output signal having a predetermined frequency cannot be stably obtained for a long period of time during the intermittent PLL driving.